FIG. 1 shows a prior art electrically erasable PROM (EEPROM) 100. It includes an n+ drain 102 and n+ source 104 formed in a p-well 106 and separated by a channel region 108. A floating gate 110 is formed over the channel region 108 and separated from the substrate 106 by a dielectric 112 in the form of a gate oxide. A control gate 114, separated from the floating gate 110 by an insulating layer 116, is formed over the floating gate 110. The floating gate 110 acts as the charge storage region for the memory device and is programmed by applying a voltage to the drain 102 and pulsing the control gate 114. This creates a high conductivity region in the channel region 108. High energy electrons (hot electrons) are accelerated across the channel region 108 and occasionally collide with lattice or dopant atoms to generate additional electron-hole pairs by impact ionization. The resultant scattered electrons occasionally have sufficient energy to bridge the gap of the dielectric 112 to the floating gate 110, being helped across by the voltage on the control gate. While programming of the cells involved hot electrons colliding with lattice and dopant atoms, erasing involves Fowler-Nordheim tunneling. In order to achieve this tunneling effect, a high electric field is established across the gate oxide 112 between the floating gate 110 and the channel 108. The effect is that during erasing of the memory cell, electrons are removed from the floating gate 110 by pulsing the drain 102 while holding the control gate 114 at ground or negative potential. The source 104 is permitted to float during erasing. The EEPROM thus has the advantage of allowing individual memory cells to be erased electronically.
FIG. 2 shows an electrically erasable PROM (EEPROM) 200, which differs from the EEPROM in FIG. 1 in that it includes a thin tunnel dielectric 202 between the drain 204 and the floating gate 206. This allows both programming and erasing by Fowler-Nordheim tunneling, which is achieved by providing a potential difference across the drain 204 and control gate 208 of the order of 20V. During programming, electrons are added to the floating gate 206 by holding the drain at ground level and pulsing the control gate 208 at 20V for about 10 ms.
In contrast, during erasing of the memory cell, electrons are removed from the floating gate 206 by pulsing the drain 204 while holding the control gate 208 at ground potential. The source 210 is permitted to float during programming and erasing. As mentioned above, the EEPROM has the advantage of allowing individual memory cells to be erased electronically. In fact, in practice all of the memory cells in an array are typically erased and thereafter select memory cells are programmed.
Yet another type of memory cell, known as the Frohmann-Bentchkowsky EPROM 300, is shown in FIG. 3 and involves only a single poly layer defining a gate 302 separated from a channel region 304 by a gate oxide layer 306. An insulating layer 310 also covers the gate 302 to completely encapsulate the gate 302, thereby defining a floating gate that acts as the charge accumulation region. A p+ drain 312 and p+ source 314 are formed in an n-well 320 or n-substrate on either side of the channel region 304 and programming of the memory cell occurs by providing a lower voltage to the drain 312 compared to the source 314 and well 320. In particular, the well 320 can be held at ground level with the source 314 at ground level, while the drain 312 is held at a negative voltage. Alternatively the drain 312 can be held at ground while the well 320 is provided with a positive voltage and the source 314 is held at the positive voltage. The effect is a high electric field across the channel region 304 which causes hot electrons to be accelerated across the channel and occasionally to generate electron hole pairs by impact ionization. Some of the electrons generated by the impact ionization bridge the gap to the floating gate 302 to establish a negative charge in the gate. However, during the erasing process, since there is no control gate, there is no way to remove the charge from the floating gate. Thus the only way to erase a memory array made of memory cells of this nature is to eradiate them with UV radiation thereby erasing all of the memory cells in the array. Thus while this structure has the advantage of making use of only a single poly layer, it suffers from the disadvantage that individual memory cells in an array cannot be separately erased and the erasing is not electrical.
In order to address this problem, a single poly EEPROM was developed as shown in FIG. 4. This prior art EEPROM includes a first PMOS involving a p+ drain 400 and a p+ source 402 in a first n-well 404 with a floating poly gate 406 formed above a channel 408 between the drain 400 and source 402. The EEPROM further includes a second PMOS comprising a p+ drain 410 and a p+ source 412 in a second n-well 414, with a floating poly 416 formed over a channel region 418 between the drain 410 and p+ source 412. By including a second capacitor as defined by the second poly 416, spaced from the channel region 418 by an oxide layer 420, the cell of FIG. 4 provides for a control gate that allows the storage capacitor (as defined by the poly 406 spaced from the channel 408 by an oxide layer) to be electrically erased. It will however be appreciated that this structure has the drawback that it requires two PMOS devices. It therefore requires a considerable amount of space as defined by the well spacing between the two PMOS devices.
The applicant has therefore developed a new structure, which is described in concurrently filed patent application entitled “NON-VOLATILE MEMORY CELL WITH FULLY ISOLATED SUBSTRATE AS CHARGE STORAGE”. In this structure, which is shown in plan view in FIG. 5 and folded out cross-section in FIG. 6, a single poly layer is used to form a control gate (CG) 512, erase/program gate (E/P G) 510 and read gate (RG) 540 formed over an isolated substrate or floating bulk (FB) 502 (that is isolated from a substrate 530 below by a buried oxide 531, and is isolated along its sides by trench oxide (deep or shallow trench) 506, and from the poly strips above by gate oxide 508. The RG 540 provides an extension 542 that extends over a second substrate region that is isolated from the FB. A drain region 520 and a source region 522 are formed in the second substrate region 532 and form a channel region 524 between them to define a read transistor 518 with the extension 542 serving as transistor poly gate. The detailed description of the structure 500 and its operation is given in the above patent application entitled “NON-VOLATILE MEMORY CELL WITH FULLY ISOLATED SUBSTRATE AS CHARGE STORAGE”, which is included herein in its entirety by reference. The one drawback that exists in the structure 500 is that it still uses up a considerably amount of space due to the need for a large CG 512 to provide the necessary capacitive coupling with the FB 502.
Thus it will be appreciated that each of the prior art devices suffers from certain disadvantages. In the EPROM cell of FIG. 3 the capacitor is defined by a floating gate separated from a well by a gate oxide, however since there is no control gate, the erasing process requires UV radiation. In contrast, all of the electrically erasable memory cells involve a control transistor and a capacitor for charge storage. For instance, in the EEPROM of FIG. 1 and EEPROM of FIG. 2 the capacitor is formed by the floating gate separated by the gate oxide from the well, and a control gate is used to control the floating gate voltage. These EEPROM devices however also suffer from disadvantages, in that the floating gate and control gate are formed from two separate poly layers. In the case of the EEPROMs of FIG. 4 and FIGS. 5 and 6 the above problem is addressed in that both these structures make use of only a single poly. However, in the case of the FIG. 4 embodiment it requires two n-wells and therefore uses up a lot of space as determined by the well-to-well spacing, while in the FIGS. 5 and 6 embodiment the large control gate consumes a considerable amount of space.
The present invention seeks to improve the memory cell density of the structures of the prior art and of the concurrently filed application shown in FIGS. 5 and 6, while maintaining the advantage of a single poly structure.